Fujitsu F2MC-8L Series, Руководство по оборудованию, Страница: 52 / 131

HARDWARE CONFIGURATION
2-32
I/O PORTS
•
Operation for input port (DDR = 0)
When used as the input port, the output impedance goes High. There-
fore, when the PDR is read, the value of the pin is read.
•
Resource input operation
This pin is used both as a resource input and as a port. The value of the
pin is always input to the port serving as the resource input (irrespective of
the setting conditions of the PDR and resource). When using an external
signal at the resource, set the DDR to 0.
•
State when reset
When reset, the DDR is initialized to 0 and the output impedance goes
High at all bits. When reset, the PDR is not initialized. Therefore, set the
value of the PDR before setting the DDR to output.
•
State in stop modes
With the SPL bit of the standby-control register set to 1, in the stop mode,
the output impedance goes High irrespective of the value of the DDR.
Internal data bus
PDR read
Stop mode (SPL = 1)
Input buffer
Output latch
DDR
PDR
PDR read
(when Read Modify Write instruction executed)
DDR write
PDR write
Pin
Resource
input
Fig. 2.16 Port 31
(8) P40 to P47: P-ch open-drain high-withstand-voltage output ports
P50 to P57: P-ch open-drain high-withstand-voltage output ports
P60 to P67: P-ch open-drain high-withstand-voltage output ports
•
Operation for output port
The value written at the PDR is output to the pin. When the PDR is read in
this port, usually, the contents of the output latch is read instead of the val-
ue of the pin.
•
State when reset
The PDR is initialized to 0 at reset, so the output register is turned off at all
bits.