Fujitsu F2MC-8L Series, Руководство по оборудованию, Страница: 127 / 131

APPENDIX
App.- 4
Address
18
H
to
7F
H
18
H
(R/W) T3CR X000 XXX0 Timer 3 control register
19
H
(R/W) T2CR X000 XXX0 Timer 2 control register
1A
H
(R/W) T3DR XXXX XXXX Timer 3 data register
1B
H
(R/W) T2DR XXXX XXXX Timer 2 data register
1C
H
(R/W) SMR 0000 0000 Serial mode register
1D
H
(R/W) SDR XXXX XXXX Serial data register
1E
H
(R/W) ADC1 0000 0000 A/D control register 1
1F
H
(R/W) ADC2 -000 0001 A/D control register 2
20
H
(R/W) ADDH 0000 00XX A/D data register (H)
21
H
(R/W) ADDL XXXX XXXX A/D data register (L)
22
H
(W) PCR0 0000 0000 Port input control register 0
23
H
(W) PCR1 - - - - 0000 Port input control register 1
24
H
(R/W) MCNT 0000 0000 MPG control register
25
H
(R/W) INTSTR 0000 0000 MPG interrupt status register
26
H
(W) CMCLBR(H) - - - - 0000 MPG compare clear buffer register (H)
27
H
(W) CMCLBR(L) 0000 0000 MPG compare clear buffer register (L)
28
H
(W) OUTCBR(H) - - - - 0000 MPG output buffer register (H)
29
H
(W) OUTCBR(L) 0000 0000 MPG output buffer register (L)
2A
H
2B
H
2C
H
Reserved — (Access disable)
2D
H
2E
H
2F
H
30
H
to 77
H
78
H
79
H
7A
H
7B
H
7C
H
(W) ILR1 1111 1111 Interrupt level setting register 1
7D
H
(W) ILR2 1111 1111 Interrupt level setting register 2
7E
H
(W) ILR3 1111 1111 Interrupt level setting register 3
7F
H
Reserved — (Access disable)
Address Read/Write Register Description of register
Initial value
MSB
⇐ ⇒
LSB
Note: The value is undefined when the bit indicated by — in the register column.
See each section describing the block of the registers for each register function.