MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
107
Document Revision History
Table 81
shows the SVR settings by device and package type.
26 Document Revision History
Table 82
provides a revision history for this hardware specification.
Table 81. SVR Settings
Device
Package
SVR
(Rev. 2.0)
SVR
(Rev. 2.1)
MPC8360E
TBGA
0x8048_0020
0x8048_0021
MPC8360
TBGA
0x8049_0020
0x8049_0021
MPC8358E
TBGA
0x804A_0020
0x804A_0021
MPC8358
TBGA
0x804B_0020
0x804B_0021
Table 82. Revision History
Rev.
Number
Date
Substantive Change(s)
4
01/2011 • Updated references to the LCRR register throughout
• Removed references to DDR DLL mode in
Section 6.2.2, “DDR and DDR2 SDRAM Output AC Timing
Specifications
.”
• Changed “Junction-to-Case” to “Junction-to-Ambient” in
Section 23.2.4, “Heat Sinks and
Junction-to-Ambient Thermal Resistance
,” and
Table 78
, “Heat Sinks and Junction-to-Ambient Thermal
Resistance of TBGA Package,” titles.
3
03/2010 • Changed references to RCWH[PCICKEN] to RCWH[PCICKDRV].
• In
Table 2
, added extended temperature characteristics.
• Added
Figure 6
, “DDR Input Timing Diagram.”
• In
Figure 53
, “Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package,”
removed watermark.
• Updated the title of
Table 19
,”DDR SDRAM Input AC Timing Specifications.”
• In
Table 20
, “DDR and DDR2 SDRAM Input AC Timing Specifications Mode,” changed table subtitle.
• In
Table 27
–
Table 30
,
and
Table 33
—
Table 34
, changed the rise and fall time specifications to reference
20–80% and 80–20% of the voltage supply, respectively.
• In
Table 38,
“IEEE 1588 Timer AC Specifications,” changed first parameter to “Timer clock frequency.”
• In
Table 45
, “I2C AC Electrical Specifications,” changed units to “ns” for t
I2DVKH
.
• In
Table 66
, “MPC8360E TBGA Pinout Listing,” and
Table 67
“MPC8358E TBGA Pinout Listing
,
added
note 7: “This pin must always be tied to GND” to the TEST pin and added a note to SPARE1 stating: “This
pin must always be left not connected.”
• In
Section 4, “Clock Input Timing
,” added note regarding rise/fall time on QUICC Engine block input pins.
• Added
Section 4.3, “Gigabit Reference Clock Input Timing
.”
• Updated
Section 8.1.1, “10/100/1000 Ethernet DC Electrical Characteristics
.”
• In
Section 21.3, “Pinout Listings
,” added sentence stating “Refer to AN3097, ‘MPC8360/MPC8358E
PowerQUICC Design Checklist,’ for proper pin termination and usage.”
• In
Section 22, “Clocking
,” removed statement: “The OCCR[PCICDn] parameters select whether CLKIN
or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.”
• In
Section 22.1, “System PLL Configuration
,” updated the system VCO frequency conditions.
• In
Table 80
, added extended temperature characteristics.
2
12/2007 Initial release.