MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
103
System Design Information
24.1
System Clocking
The device includes two PLLs, as follows.
•
The platform PLL (AV
DD
1) generates the platform clock from the externally supplied CLKIN
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in
Section 22.1, “System PLL Configuration.”
•
The e300 core PLL (AV
DD
2) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL
ratio configuration bits as described in
Section 22.2, “Core PLL Configuration.”
24.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AV
DD
1,
AV
DD
2, respectively). The AV
DD
level should always be equivalent to V
DD
, and preferably these voltages
will be derived directly from V
DD
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in
Figure 56
, one to each of the five AV
DD
pins. By
providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
DD
pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
DD
pin, which is on the periphery of package, without the inductance of vias.
Figure 56
shows the PLL power supply filter circuit.
Figure 56. PLL Power Supply Filter Circuit
24.3
Decoupling Recommendations
Due to large address and data buses as well as high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each V
DD
, OV
DD
, GV
DD
, and LV
DD
pins of the device. These
decoupling capacitors should receive their power from separate V
DD
, OV
DD
, GV
DD
, LV
DD
, and GND
V
DD
AV
DD
n
2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
10
Ω
