Freescale Semiconductor MC9S12XHY Series, Справочное руководство

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Electrical Characteristics
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor 755
In Figure A-10 the timing diagram for master mode with transmission format CPHA=1 is depicted.
Figure A-10. SPI Master Timing (CPHA = 1)
In Table A-26 the timing characteristics for master mode are listed.
Table A-26. SPI Master Mode Timing Characteristics
Num C Characteristic
Sym
bol
Min Typ Max Unit
1 D SCK frequency f
sck
f
bus
/2048 —
MIN(16, f
bus
/2)
1
1
SPI on non-motor pad ports (Port S or Por t H)
MHZ MIN(10,f
bus
/2)
2
2
SPI on Port V with slew rate control disable. All the SPI pins slew rate control should be disabled.
MIN(0.8,f
bus
/2)
3
3
SPI on Port V with slew rate control enabled. All the SPI pins slew rate control should be enabled.
4. MIN(16, f
bus
/2) means select minimum frequency value from 16MHZ and f
bus
/2MHZ. same for the other MIN(X,Y)
5. MAX(62.5, 2*t
bus
) means select the maximum period value from 62.5ns and 2*t
bus
ns. same for the other MAX(X,Y)
1 D SCK period t
sck
MAX(62.5, 2*t
bus
)
1
—
2048 ∗
t
bus
ns MAX(100, 2*t
bus
)
2
MAX(1250, 2*t
bus
)
3
2 D Enable lead time t
lead
— 1/2 — t
sck
3 D Enable lag time t
lag
— 1/2 — t
sck
4 D Clock (SCK) high or low time t
wsck
— 1/2 — t
sck
5 D Data setup time (inputs) t
su
8 — — ns
6 D Data hold time (inputs) t
hi
8 — — ns
9 D Data valid after SCK edge t
vsck
— — 29 ns
10 D Data valid after SS fall (CPHA = 0) t
vss
— — 15 ns
11 D Data hold time (outputs) t
ho
20 — — ns
12 D Rise and fall time inputs t
rfi
— — 8 ns
13 D Rise and fall time outputs t
rfo
— — 8 ns
SCK
(Output)
SCK
(Output)
MISO
(Input)
MOSI
(Output)
1
5 6
MSB IN2
Bit MSB-1. . . 1
LSB IN
Master MSB OUT2
Master LSB OUT
Bit MSB-1. . . 1
4 4
9
12 13
11
Port Data
(CPOL = 0)
(CPOL = 1)
Port Data
SS
(Output)
2 12 13 3
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
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