Freescale Semiconductor ColdFire MCF5211, Справочное руководство

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General Purpose I/O Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor 11-5
11.6.2 Port Data Direction Registers (DDR n)
The DDR n registers control the direction of the port n pin drivers when the pins are configured for digital
I/O.
The DDR n registers with a full 8-bit implementation are shown in Figure 11-7 . The remaining DDR n
registers use fewer than eight bits. Their bit definitions are shown in Figure 11-8 , Figure 11-9 ,
Figure 11-10 , and Figure 11-11 . The fields are described in Table 11-3 , which applies to all DDR n
registers.
The DDR n registers are read/write. At reset, all bits in the DDR n registers are cleared.
IPSBAR
Offset: 0x10_000D (PORTQS)
Access: User read/write
7 6 5 4 3 2 1 0
R 0
PORT n 6 PORT n 5 PORT n 4 PORT n 3 PORT n 2 PORT n 1 PORT n 0
W
Reset: 0 1 1 1 1 1 1 1
Figure 11-4. Port QS Output Data Register (PORTQS)
IPSBAR
Offset: 0x10_0008 (PORTNQ)
Access: User read/write
7 6 5 4 3 2 1 0
R
PORT n 7 PORT n 6 PORT n 5 PORT n 4 PORT n 3 PORT n 2 PORT n 1
0
W
Reset: 1 1 1 1 1 1 1 0
Figure 11-5. Port NQ Output Data Register (PORTNQ)
IPSBAR
Offset: 0x10_000B (PORTAS)
Access: User read/write
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
PORT n 1 PORT n 0
W
Reset: 0 0 0 0 0 0 1 1
Figure 11-6. Port AS Output Data Register (PORTAS)
Table 11-2. PORT n Field Descriptions
Field Description
Port n x Data to be driven when the port pin is configured as a digital output.
1 Output is a logic “1”
0 Output is a logic “0”