Freescale Semiconductor ColdFire MCF5211, Справочное руководство

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General Purpose I/O Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor 11-9
11.6.4 Port Clear Output Data Registers (CLR n )
Writing 0s to a CLR n register clears the corresponding bits in the PORT n register. Writing 1s has no effect.
Reading the CLR n register returns 0s.
The CLR n registers with a full 8-bit implementation are shown in Figure 11-17 . The remaining DDR n
registers use fewer than eight bits. Their bit definitions are shown in Figure 11-18 , Figure 11-19 ,
Figure 11-20 , and Figure 11-21 . The fields are described in Table 11-5 , which applies to all CLR n
registers.
The CLR n registers are read/write.
Table 11-4. PORT n P/SET n Field Descriptions
Field Description
Port n Px Port n x pin data/set data bits.
1 Port n Px pin state is “1” (read); writing a 1 sets the corresponding port n x bit to “1”
0 Port n Px pin state is “0”
IPSBAR
Offsets:
0x10_0045 (CLRDD)
0x10_0046 (CLRAN) Access: User read/write
7 6 5 4 3 2 1 0
R
CLR n 7 CLR n 6 CLR n 5 CLR n 4 CLR n 3 CLR n 2 CLR n 1 CLR n 0
W
Reset: 0 0 0 0 0 0 0 0
Figure 11-17. Port Clear Output Data Registers with Bits 7:0 Implemented (CLRDD, CLRAN)
IPSBAR
Offsets:
0x10_004A (CLRTA)
0x10_004B (CLRTC)
0x10_004C (CLRTD)
0x10_004D (CLRUA)
0x10_004E (CLRUB)
0x10_004F (CLRUC) Access: User read/write
7 6 5 4 3 2 1 0
R 0 0 0 0
CLR n 3 CLR n 2 CLR n 1 CLR n 0
W
Reset: 0 0 0 0 0 0 0 0
Figure 11-18. Port Clear Output Data Registers with Bits 3:0 Implemented (CLRTA, CLRTC, CLRTD, CLRUA,
CLRUB, CLRUC)