Freescale Semiconductor ColdFire MCF5211, Справочное руководство

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UART Modules
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor 21-21
21.4.2.3 FIFO
The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding registers.
The receive buffer consists of the FIFO and a receiver shift register connected to the U
n RXD (see
Figure 21-18 ). Data is assembled in the receiver shift register and loaded into the top empty receiver
holding register position of the FIFO. Therefore, data flowing from the receiver to the CPU is
quadruple-buffered.
In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break
(RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By
programming the ERR bit in the UART’s mode register (UMR1
n ), status is provided in character or block
modes.
USR n [RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive
buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the
FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom
of the FIFO. The FIFO-full status bit (FFULL) is set if all three positions are filled with data. The RXRDY
or FFULL bit can be selected to cause an interrupt and TXRDY or RXRDY can be used to generate a DMA
request.
The two error modes are selected by UMR1 n [ERR]:
• In character mode (UMR1 n [ERR] equals 0, status is given in the USR n for the character at the top
of the FIFO.
• In block mode, the USR n shows a logical OR of all characters reaching the top of the FIFO since
the last
RESET ERROR STATUS
command. Status is updated as characters reach the top of the FIFO.
Block mode offers a data-reception speed advantage where the software overhead of
error-checking each character cannot be tolerated. However, errors are not detected until the check
is performed at the end of an entire message—the faulting character is not identified.
In either mode, reading the USR n does not affect the FIFO. The FIFO is popped only when the receive
buffer is read. The USR n should be read before reading the receive buffer. If all three receiver holding
registers are full, a new character is held in the receiver shift register until space is available. However, if
a second new character is received, the contents of the character in the receiver shift register is lost, the
FIFOs are unaffected, and USR
n [OE] is set when the receiver detects the start bit of the new overrunning
character.
To support flow control, the receiver can be programmed to automatically negate and assert U n RTS, in
which case the receiver automatically negates U n RTS when a valid start bit is detected and the FIFO is
full. The receiver asserts U n RTS when a FIFO position becomes available; therefore, connecting U n RTS
to the U n CTS input of the transmitting device can prevent overrun errors.
NOTE
The receiver continues reading characters in the FIFO if the receiver is
disabled. If the receiver is reset, the FIFO, U
n RTS control, all receiver status
bits, and interrupts, and DMA requests are reset. No more characters are
received until the receiver is reenabled.