Freescale Semiconductor ColdFire MCF5211, Справочное руководство

Страница: 106 / 544

Clock Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual , Rev. 3
6-2 Freescale Semiconductor
6.3.2 1:1 PLL Mode
In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency.
The post divider is not active.
6.3.3 External Clock Mode
In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting
operating frequency is equal to the external clock frequency.
6.4 Low-Power Mode Operation
This subsection describes the operation of the clock module in low-power and halted modes of operation.
Low-power modes are described in
Chapter 7, “Power Management.” Table 6-1 shows the clock module
operation in low-power modes.
Table 6-1. Clock Module Operation in Low-power Modes
In wait and doze modes, the system clocks to the peripherals are enabled and the clocks to the CPU and
SRAM are stopped. Each module can disable its clock locally at the module level.
In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL
or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time.
The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator
can also be disabled during stop mode, but requires a wakeup period to restart.
When the PLL is enabled in stop mode (STPMD[1:0]), the external CLKOUT signal can support systems
using CLKOUT as the clock source.
There is also a fast wakeup option for quickly enabling the system clocks during stop recovery. This
eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system.
To prevent a non-locked PLL frequency overshoot when using the fast wakeup option, change the RFD
divisor to the current RFD value plus one before entering stop mode.
In external clock mode, there are no wakeup periods for oscillator startup or PLL lock.
6.5 Block Diagram
Figure 6-1 shows a block diagram of the entire clock module.
Low-power Mode Clock Operation Mode Exit
Wait Clocks sent to peripheral modules only Exit not caused by clock module, but normal
clocking resumes upon mode exit
Doze Clocks sent to peripheral modules only Exit not caused by clock module, but normal
clocking resumes upon mode exit
Stop All system clocks disabled Exit not caused by clock module, but clock
sources are re-enabled and normal
clocking resumes upon mode exit
Halted Normal Exit not caused by clock module