Freescale Semiconductor ColdFire MCF5211, Справочное руководство

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General Purpose I/O Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor 11-7
11.6.3 Port Pin Data/Set Data Registers (PORT n P/SET n )
The PORT n P/SET n registers reflect the current pin states and control the setting of output pins when the
pin is configured for digital I/O.
The PORT n P/SET n registers with a full 8-bit implementation are shown in Figure 11-12 . The remaining
PORT n P/SET n registers use fewer than eight bits. Their bit definitions are shown in Figure 11-13 ,
Figure 11-14 , Figure 11-15 , and Figure 11-16 . The fields are described in Table 11-4 , which applies to all
PORT n P/SET n registers.
The PORT n P/SET n registers are read/write. At reset, the bits in the PORT n P/SET n registers are set to the
current pin states.
Reading a PORT n P/SET n register returns the current state of the port n pins.
Writing 1s to a PORT n P/SET n register sets the corresponding bits in the PORT n register. Writing 0s has
no effect.
IPSBAR
Offset: 0x10_001F (DDRAS)
Access: User read/write
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
DDR n 1 DDR n 0
W
Reset: 0 0 0 0 0 0 0 0
Figure 11-11. Port AS Data Direction Register (DDRAS)
Table 11-3. DDR n Field Descriptions
Field Description
DDR n x Sets data direction for port n x pin when the port is configured as a digital output.
1 DDR n x is configured as an output
0 DDR n x is configured as an input
IPSBAR
Offsets:
0x10_0031 (PORTDDP/SETDD)
0x10_0032 (PORTANP/SETAN) Access: User read/write
7 6 5 4 3 2 1 0
R
PORT n P7 PORT n P6 PORT n P5 PORT n P4 PORT n P3 PORT n P2 PORT n P1 PORT n P0
W
Reset: 1 1 1 1 1 1 1 1
Figure 11-12. Port Pin Data/Set Data Registers with Bits 7:0 Implemented (PORTDD/SETDD,
PORTAN/SETAN)