7.2.4 Software Version Register (CPLD_SWVER)
Address: 0h base + 3h offset = 3h
Bit
0
1
2
3
4
5
6
7
Read
SW_VER
Write
Reset
x*
x*
x*
x*
x*
x*
x*
x*
* Notes:
x depends on actual board setting.x = Undefined at reset.
•
CPLD_SWVER field descriptions
Field
Description
0–7
SW_VER
7.2.5 Reset Control Register (CPLD_RSTCON)
Address: 0h base + 10h offset = 10h
Bit
0
1
2
3
4
5
6
7
Read
GE2RST
GE1RST
Reserved
SW_RST
Write
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
CPLD_RSTCON field descriptions
Field
Description
0
GE2RST
GE PHY2 reset. Write 1 to clear.
0
No reset occurs
1
GE PHY2 reset signal is produced
1
GE1RST
GE PHY1 reset. Write 1 to clear.
0
No reset occurs
1
GE PHY1 reset signal is produced
2–6
-
This field is reserved.
Reserved.
7
SW_RST
Software reset. Write 1 to clear.
0
No reset occurs
1
CPU reset occurs
CPLD Memory Map/Register Definition
C29x PCIe Card User Guide, Rev. 0, 10/2013
46
Freescale Semiconductor, Inc.
Содержание C29x
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