TCK/TSTCLK
SYSCLK
(66 MHz - 100 MHz)
(207 MHz - 400 MHz)
RTC/CORE_BYPASS_CLK
COP
DDR_CLK
DDR PHY
PLL
(800 MHz - 1300 MHz)
SDHC_CLK
SPI_CLK
IIC[1-2]_SCL
PLL
Lynx(x4)
SD_REF_CLK_B
(100 MHz or 125 MHz)
SD_REF_CLK
(100 MHz or 125 MHz)
EC_GTX_CLK125
EC_MDC
TSEC_GTX_CLK
TSEC_RX_CLK
eTSEC
DDR
/4, 8, /16
MCK_B
MCK
LCK[0:1]
(10 MHz - 100 MHz)
IFC
SAP
tck_nog
tck
PLL
e500 Core
Complex
L2
idcp_ipg_clk
div
PLL
SPI
eSDHC
I2C
CAAMs,
Other IPs
PCI-EX
div
Figure 3-1. C29x PCIe input clocks
In the above figure:
• SYSCLK is a 66.67 MHz primary clock
• DDR_CLK is 100 MHz external clock
• SD_REFCLK is 100 MHz, required for PCIe interface
• TSEC_RX_CLK is 125 MHz, required for GE port
• CPLD_REFCLK is 32.768 kHz, required for CPLD to work
Resets
C29x PCIe Card User Guide, Rev. 0, 10/2013
20
Freescale Semiconductor, Inc.
Содержание C29x
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