Freescale Semiconductor C29x, Руководство пользователя

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Chapter 6
POR Configuration
The C29x PCIe card has user selectable switches or registers, for evaluating different
frequency and boot configuration for this device. The table below shows how POR
configuration is done through switches.
Table 6-1. POR configuration through switches
Switch POR
configuration
Signal name Default
setting
Signal meaning Settings
SW4[1] cfg_sys_pll[0] IFC_AD0 ON Rate between
SYSCLK input and
CCB clock (platform
clock) SW4[1,2,3] ON ON ON (000): 4:1
SW4[1,2,3] ON ON OFF (001): 5:1
SW4[1,2,3] ON OFF ON (010): 6:1
Others are reserved.
SYSCLK on this board is 66.67 MHz.
SW4[2] cfg_sys_pll[1] IFC_AD1 OFF
SW4[3] cfg_sys_pll[2] IFC_AD2 ON
SW4[4] cfg_sys_speed READY OFF 0: SYSCLK frequency is at or below 66
MHz.
1: SYSCLK frequency is above 66
MHz.
SW4[5] cfg_core_pll[0] IFC_AD3 OFF Ratio between the
e500 core clock and
e500 CCB clock SW4[5,6,7] ON ON ON (000): reserved
SW4[5,6,7] ON ON OFF (001):
reserved
SW4[5,6,7] ON OFF ON (010): 1:1
SW4[5,6,7] ON OFF OFF (011): 1.5:1
SW4[5,6,7] OFF ON ON (100): 2:1
SW4[5,6,7] OFF ON OFF (101): 2.5:1
SW4[5,6,7] OFF OFF ON (110): 3:1
SW4[5,6,7] OFF OFF OFF (111): 3.5:1
SW4[6] cfg_core_pll[1] IFC_AD4 ON
SW4[7] cfg_core_pll[2] IFC_AD5 ON
SW4[8] cfg_core_speed IFC_AD6 ON Core speed
configuration input ON(0): Core clock frequency is greater
than or equal to 600 MHz and less than
1001 MHz.
OFF(1): Core clock frequency is
greater than or equal to 1001 MHz and
less than 1201 MHz.
SW5[1] SW_CFG_ROM_
LOC0 OFF Boot ROM location SW5[1:4] ON ON OFF ON (0010): 8b
NAND (8k page size)
Table continues on the next page...
C29x PCIe Card User Guide, Rev. 0, 10/2013
Freescale Semiconductor, Inc. 35