Fostex VR800, Руководство по обслуживанию

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VR800 / VR800Z
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4-5-5. Adat In/Out Check
By connecting the DATA IN and OUT terminals, this tests
checks if the ADAT digital signal output by itself is correctly
received. If the PLL circuit is not in a “LOCKED” condition,
the prompt below will be displayed.
The following is considered to be the cause of problem.
• Defect on DIGITAL OUT
- No oscillation of resonator X1.
- Connector J4, gate array U5, U20 and / or surrounding
circuit are defective.
• Defect on DIGITAL IN
- Connector J5, gate array U5, U20 and / or surrounding
circuit are defective.
- PLL circuit (U22, 23, 35, 36, 37, 38, 39 and / or
surrounding circuit) are defective.
• The SETUP “DIGITAL IN” is set other than “L: - R: -”.
Even if the before mentioned prompt is displayed, pressing the [EXECUTE/YES] key would reach the next test.
4-5-6. Vari-Pitch Circuit Check
Using the master clock generated through the VR800 vari-pitch
circuit on the MAIN PCB, the adat digital signal is output. This
test checks if the adat digital signal output by itself is correctly
received. If not, it means that the vari-pitch circuit does not work
correctly. As a result, the prompt below will be displayed.
The following is considered to be the cause of problem.
• Defects on the vari-pitch circuit (U3, U9), gate array (U5)
and / or surrounding circuit.
Even if the before mentioned prompt is displayed, pressing the [EXECUTE/YES] key would reach the next test.