Copyright
©
2015
congatec
AG
PA3Cm11
35/81
14
GND
15
CAM0_
CSI2 Camera 0 Differential Clock+ (Strobe)
16
CAM0_CSI_CLK-
CSI2 Camera 0 Differential Clock- (Strobe)
17
GND
18
CAM0_I2C_CLK
Camera 0 Control Interface, CLK
19
CAM0_I2C_DAT
Camera 0 Control Interface, DATA
20
CAM0_ENA#
Camera 0 Enable (low active)
21
MCLK
Master Clock. May be used to drive camera's internal PLL (19.2MHz or 25MHz)
22
CAM1_ENA#
Camera 1 Enable (low active)
23
CAM1_I2C_CLK
Camera 1 Control Interface, CLK
24
CAM1_I2C_DAT
Camera 1 Control Interface, DATA
25
GND
26
CAM1_
CSI2 Camera 1 Differential Clock+ (Strobe)
27
CAM1_CSI_CLK-
CSI2 Camera 1 Differential Clock- (Strobe)
28
GND
29
CAM1
CSI2 Camera 1 Data Lane 0+
30
CAM1_CSI_D0-
CSI2 Camera 1 Data Lane 0-
31
CAM1_RST#
Camera 1 Reset (low active)
32
CAM1
N.C.
33
CAM1_CSI_D1-
N.C.
34
GND
35
CAM0_GPIO
GPIO for Camera 0
36
CAM1_GPIO
GPIO for Camera 1
Note
The MIPI interface fuse limits the power budget by 750 mA hold current.