Fluke 9100A Series, Руководство пользователя

Страница: 40 / 122

9100A-017
4-16
becomes critical as clock speeds increase above 5 Mhz. This
duty cycle ensures that the the minimum clock pulse width of 50
ns is maintained. If the clock does not have a duty cycle close to
50%, the external sync mode is recommended instead of the
capture mode for high speeds.
When capture clock is used, performing the external calibration
procedure (described earlier in this section) is recommended. If
a UUT has considerable propagation delay, the TL/1
setoffset
command can adjust for this. (The sync mode must be set to
“capture” prior to using the
setoffset command.)
SYNCHRONIZING MULTIPLE MODULE VECTORS 4.17.
To synchronize the output vectors of multiple modules, the same
clock source must be applied to the DR CLK input of all the
modules that are to be synchronized. The INT CLK clock
(selectable at 1, 5, 10, or 20 MHz) may be used as the clock
source by connecting it to the DR CLK input of all modules. An
external clock at any frequency may also be used (external clock
signals must meet the specifications listed in Section 2).
As the speed of the clock increases, high-speed signal tech-
niques must be used to ensure signal integrity. A connector made
of high-quality cabling with each set of signal and ground lines
the same length gives good results. In some cases, providing a
separate buffered clock signal to each DR CLK input may be
necessary.