Fluke 863, Руководство по обслуживанию

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867B,863
Service Manual
2-22
Glitch Capture 2-42.
A brief spike (glitch) on the input signal can be used to trigger the GMM for a single
waveform acquisition. Glitch capture thresholds are fixed at
±
10% of the full scale value
of the waveform display. For example, in the 3V range the full scale value of the
waveform display is approximately
±
5V. Therefore, the glitch capture thresholds are
±
0.5V. A positive or negative input glitch crossing either of these thresholds causes a
trigger.
The input signal to the glitch capture circuit originates at the second AC amplification
stage output (TP23.) This signal is routed to a bandpass filter (R38, C30, C102, and
R102), through U30, and on to the comparators. DAC1 and DAC2 generate fixed
threshold levels for each comparator. The DAC1 output value is inverted within U30 and
applied to the positive input of the comparator; this arrangement sets a negative lower
trigger threshold. A trigger is generated when either a positive or negative signal from
the bandpass filter crosses the appropriate threshold.
Single Shot 2-43.
Single shot enables the user to capture a single event. Either the single level or dual level
trigger circuits can be used. There are no circuit differences external to U30.
Frequency Trigger 2-44.
The trigger circuitry also provides transitions so that the digital ASIC can measure
frequency. The dual threshold trigger circuitry is normally used to provide transitions for
frequency measurement; the thresholds set for triggering also become the thresholds used
for frequency measurement.
If the single threshold trigger has been selected, the thresholds used for frequency
measurement are fixed and are not related to the threshold used for triggering the
waveform acquisition; fixed levels applied to the dual level trigger circuitry establish the
trigger thresholds for frequency measurement only.
Logic Activity Trigger 2-45.
Transitions generated by the dual threshold trigger circuit are used by the digital ASIC to
measure logic signal frequency. DAC1 and DAC2 fix the trigger threshold voltages
based on the type of logic (TTL, +3V CMOS, or +5V CMOS) you select.
Peak Hold 2-46.
The GMM displays the maximum and minimum readings acquired by the Fast A/D
Converter (U10) when Peak Hold is activated. While Peak Hold is active, waveform
displays are not available and measurements are limited to a band width of 1 MHz. The
Peak Hold filter (R144 and C99) is switched into the signal path by analog switch U14-3,
U14-4, U14-5, and U14-9.
Auto Diode 2-47.
In the Auto Diode, the GMM displays the voltage drop across a diode and shows a
picture indicating polarity encountered. The Fast A/D Converter records data that
describes the waveform of the voltage across the diodes under test. A waveform is not
displayed to the user. A software algorithm determines the polarity of the diodes. The
AC signal sourced to the input terminal is generated in the same manner as the AC signal
used for the Component Test function.