FIC PA-2010+, Руководство пользователя, Страница: 61 / 76

PA-2010+ Mainboard Manual
SDRAM Single/Burst Write
When set at Burst (write), the data will be written into the SDRAM by the
memory controller on the consecutive clock cycles.
The options are: Burst (Default), Single.
SDRAM Cycle Length
This feature appears only when SDRAM DIMM/s is installed (BIOS auto
dection). If the CAS latency of your SDRAM DIMM is 2, set at 2 to enhance
the system performance. If the CAS latency of your SDRAM DIMM is 3,
stay with the default setting, 3.
The options are: 2, 3 (Default).
SDRAM Bank Interleave
This feature appears only when SDRAM DIMM/s is installed (BIOS auto
dection). When the bank interleave fucntion of the SDRAM is enabled, its
the data transacting performance is better than when it is disabled.
The options are: 2 Bank, 4 Bank, Disabled (Default).
CPU to PCI Write Buffer
When enabled, allows data and address access to the internal buffer of
82C586 so the processor can be released from the waiting state.
The options are: Enabled (Default), Disabled.
PCI Dynamic Bursting
When enabled, the PCI controller allows Bursting PCI transfer if the
consecutive PCI cycles come with the address falling in same 1KB space.
This improves the PCI bus throughput.
The options are: Enabled (Default), Disabled.
PCI Burst
When enabled, data transfer on PCI Buses will improve. Disable this item
during trouble-shooting.
The options are: Disabled, Enabled (Default).
PCI Master 0 WS Write
When enabled, allows a zero-wait-state-cycle delay when the PCI master
drive writes data to DRAM.
The options are: Enabled (Default), Disabled.
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