FIC PA-2010+, Руководство пользователя, Страница: 59 / 76

PA-2010+ Mainboard Manual
Video
BIOS
Cacheable
When enabled, allows the system to use the video BIOS codes from SRAMs.
The options are: Enabled (Default), Disabled.
System BIOS Cacheable
When enabled, allows the ROM area F000H-FFFFH to be cacheable when
cache controller is activated. The options are: Disabled (Default), Enabled.
Memory Hole At 15MB Addr.
When enabled, the memory hole at the 15MB address will be relocated to
the 15~16MB address range of the ISA cycle when the processor accesses
the 15~16MB address area. When disabled, the memory hole at the 15MB
address will be treated as a DRAM cycle when the processor accesses the
15~16MB address. The options are: Enabled, Disabled (Default).
Sustained 3T Write
When enabled, allows the CPU to compele the memory writes in 3 clocks.
The options: Enabled (Default), Disabled.
CPU Pipeline
When enabled, allows the CPU to execute the pipeline function.
The options: Enabled (Default), Disabled.
Memory ECC Check
Allows to select different error check mode provided by your memory
modules.
The options: Disabled (Default), Enabled.
44