Fastwel AIC324, Руководство пользователя

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User Manual
AIC 324
+14 R\W Control of ADC clocking
Bit # 7 6 5 4 3 2 1 0
Name
х х х х
x CLKSEL CLKEN DMAEN
Bit DMAEN resolution for DMA channel operation at ADC data acquisition with the use of FIFO.
Bit CLKEN
рclocking resolution of ADC conversion start. If bit = 0, then ADC start is possible only by writing to the
relevant bit of the board register.
Bit CLKSEL = 0, ADC start over the negative edge from the DIN3\EXTCLK output. =1, start over the negative edge
from the output of timer/counter 2 8254. The counter 2 functions together with the counter 1 8254.
+15 R\W Configuration of ADC conversion parameters
Bit # 7 6 5 4 3 2 1 0
Name RANGE ADBU G1 G0 SCINT1 SCINT0 S\D1 S\D0
Bits S\D1-0 define operation mode of ADC ingress switches. 0
– differential inputs, 1 – standard inputs. Bit 0 sets the
configurations for 0-7 and 16-23 channels, bit 1
– 8-15 and 24-31. Bit 0 – is controlled by jumper J21, bit 1 – J22.
Jumper’s position “open” corresponds to the logical unit.
Bits SCINT1-0 set the interval of channel switching in scanning mode.00
– 20 μs, 01 – 15 μs, 10 – 10 μs, 11 – 4 μs.
Bits G1-G0 set the gain ratio of ADC path from 1 to 8.
Bits RANGE and ADBU set the ADC operation mode.
RANGE = 1 range of ADC conversion 10V, =0 range of ADC conversion to 5V.
ADBU = 0 bipolar conversion mode, = 1 unipolar conversion mode.
1.3.7 Page 4
– additional digital port
+12 R Reading the FPGA outputs from the additional D port
Bit # 7 6 5 4 3 2 1 0
Name 0 0 D5 D4 D3 D2 D1 D0
Bits D5-0 reading the state of the FPGA outputs of the additional D port. Direction of I/O of the D port is defined by the
direction of output of the most significant and the least significant registers of the C 8255 port. Direction of the C port of
the lower part determines the direction of operation for the D3..0 registers. The direction of the C port of the upper part
determines direction of the operation for registers D5..4.
+12 W Writing data to additional port D
Bit # 7 6 5 4 3 2 1 0
Name
х х
D5 D4 D3 D2 D1 D0
Bits D5-0 writing to the additional port D. The direction of input/output of port D output is determined by the direction of
output of the upper and lower registers of port C 8255. The direction of the C port of the lower part determines the
direction of work for registers D3..0. The direction of C port of the upper part determines the direction of work for
registers D5..4.
1.3.8 Page 5
– DAC control
+12 R\W Lower address of the DAC buffer
Bit# 7 6 5 4 3 2 1 0
Name DACA7 DACA6 DACA5 DACA4 DACA3 DACA2 DACA1 DACA0
Bits DACA7-0 Address for writing the DAC data to the circular signal generation buffer with the use of DAC. Buffer
length is 1024 DAC readouts. Code and number of DAC channel are written.