User Manual
AIC 324
+6
W
Write 8 lower DAC bits
Bit #
7
6
5
4
3
2
1
0
Name
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
8 lower DAC bits
+7
W
Write 8 higher DAC bits
Bit #
7
6
5
4
3
2
1
0
Name
DAC15
DAC14
DAC13
DAC12
DAC11
DAC10
DAC9
DAC8
8 higher DAC bits.
*Write leads to different results depending on the control bits status.
If DASIM = 1, write occurs to memory cell with the DAC channel number, data output to DAC is not done.
If DASIM = 0, current written value is additionally sent to DAC.
If bit DAGEN = 1, the data are written to FIFO. This write to FIFO operation has priority over DASIM bit.
+8
R
Current page and power control
Bit #
7
6
5
4
3
2
1
0
Name
0
PWREN
0
0
0
P2
P1
P0
Bits P2-0 set page for the mode of extended access to the ports of the module. The page consists of
4 registers and is mapped to 12-15 registers of the main IO area.
Bit PWREN = 1
– Power is supplied to analog part of the module (default value).
+8
W
Setting current page, power and module reset control
Bit #
7
6
5
4
3
2
1
0
Name
0
PWREN
INTRST
RESETD
RESETA
P2
P1
P0
Bits P2-0 set page for the mode of extended access to the ports of the module. The page consists of
4 registers and is mapped to 12-15 registers of the main IO area.
Bit RESETA
– Reset of DAC, FIFO, DIO and all internal registers. 8254 timer(s) is not reset.
Bit RESETD
– The same reset as RESETA, but DAC is not affected.
Bit INTRST
– Interrupts reset.
Bit PWREN = 1
– Power is supplied to analog part of the module (default value).
+9
R
Read galvanically isolated digital inputs
Bit #
7
6
5
4
3
2
1
0
Name
0
0
Debounce
DINTE
DIN3
DIN2
DIN1
DIN0
Bits DIN3-0
– Read digital inputs at analog connector.
Bit DINTE
– Enable interrupt from digital IO.
Bit Debounce
– Enable software debounce at Din[3] input. In case of bad signal, leads to possibility of the
interrupt setting jitter of 6.4
μs max.
