51
PicoBlaze reads the data at sub address 0x60 this status bit is cleared. The USB host
does not have a similar status bit; however it can be safely assumed that the PicoBlaze will
process characters as fast as they come in, as long as no transmission occurs between
the carriage-return that completes a command and the receipt of the carriage-return that
completes the response to that command. When the PicoBlaze starts its response to the
host, the first character of the response is written to sub address 0x61 and the value 0x01
is written to sub address 0x62. The PicoBlaze has another status bit, bit 4 of register
0xFC, which indicates when the host has read the value in sub address 0x61. The bit is
set when response data is written by the PicoBlaze and cleared when it is read by the USB
host. Once the host has read each response byte, the PicoBlaze continues to place new
characters at sub address 0x61 until the message is completed with an unescaped
carriage-return. The host can assume that once the value 0x01 is in sub address 0x62 it
can continue to read characters from 0x61 as fast as it can until it receives a carriage-
return. When the PicoBlaze has finished the response, it writes 0x00 to sub address 0x62
and returns to the host service loop.
"F
GET
8"
S
PEED
-
UP LOGIC
Because the PicoBlaze runs relatively slow, there is a small sequencer to speed up FPGA
configuration and flash data read. This is kicked off by a write to register 0xfe with bit 6
set. The sequencer runs the flash clock for 8 cycles, and if the FPGA CCLK was high,
copies the flash DOUT output to the FPGA configuration DIN input cycling the FPGA
CCLK 8 cycles as well. The PicoBlaze is responsible for making sure the flash is in the
appropriate state when this sequencer is started. Generally it only speeds up the inner
loop of FPGA configuration and flash data read, but this is where the largest time is spent.
Using the algorithm from previous PicoBlaze designs (Video Combiners) and bit wiggling,
the best data rate for FPGA download would be about 1.5 MHz for CCLK. With the
"Fget8" speed-up logic the rate should be about 9 MHz. This allows even large FPGAs to
be loaded in less than 2 seconds.
P
ICO
B
LAZE
M
EMORY
M
AP
Address
Description
000 - 1FF
Camera state storage. Sensor registers
shadow locations in 000 - 0FF
200 - 3FF
Header storage. Loaded from flash page 00
at power-up.
400 - 6F7
Working memory for host commands.
