31
REFERENCE FOR THE FC13 AND FC40 CAMERAS
The FC13 and FC40 cameras are based on a three FPGA design, a Control FPGA which
controls the timing of the sensor, a Data FPGA which handles specialized Data processing
functions and communication of results via USB or camera link, and a DDR FPGA which
controls the memory functions of the camera. In the USB version of the camera data flows
from the sensor to the data FPGA, then on to the DDR FPGA. From the DDR FPGA the
readout (preview and upload) takes data from memory and passes it back to the host. (The
writing and readout are asynchronous).
There are two separate sections in the DDR FPGA which provide the functionality of the
camera, the writer and the reader.
C
ONTROL
FPGA
The following sections describe the Control FPGA in the FC13 and the FC40. It contains
an overview of functionality and some design details. Essentially the same design is used
on the FC13 and the FC40 cameras.
Sensor Control
L
INE
T
IMING
Sensor line and frame rates are controlled by the Camera State settings. The minimum
line period depends on the sensor type and the ROI width. When the Line Period setting
exceeds the minimum period, extra clocks are inserted between lines. The Line Valid
period only depends on the ROI width and sensor type. The number of columns read from
the sensor is always a multiple of 10 for the MV13 and 16 for the MV40 sensor. Since the
Data FPGA also has access to the ROI settings it is possible for the actual ROI width (as
sent to the frame grabber) to start and end on any pixel, however this is not implemented.
The Control FPGA ensures that the starting and ending pixels of the ROI are read from the
sensor. For the MV13 this means as many as 9 pixels before and 9 pixels after the ROI
could be read from the sensor, depending on the starting and stopping pixel values modulo
10. For the MV40 sensor as many as 15 pre- and post-ROI pixels could be read from the
sensor, depending on the starting and stopping pixel values modulo 16. The software GUI
is responsible for determining the actual number of pixels per line based on the sensor and
readout mode.
Camera-Link or USB readout rate can be the limiting factor for the line rate in non-memory
modes. In this case it is the GUI's responsibility to maintain the Line Period setting large
enough to prevent FIFO overrun in the Data FPGA.
F
RAME
T
IMING
