56
obviously be overwritten without affecting the sensor registers if the sensor register write
enable bit is off. The layout of these registers intentionally matches the flash state storage.
0
X
24
S
TART
P
IXEL
,
LOW
8
BITS
.
0
X
25
S
TART
P
IXEL
,
HIGH
8
BITS
.
This is the leftmost pixel in the ROI. Pixels are numbered from 0 to the sensor width - 1.
This is different from the old ROI settings which worked in pixel clocks. The sensor control
logic handles the conversion from pixels to clocks. If the starting pixel is not a multiple of
the sensor readout width (10 for MV13 or 16 for MV40) there will be some prescan pixels
in the resultant image. In the future we may want to add logic in the data FPGA to mask
out the prescan pixels.
0
X
26
E
ND
P
IXEL
,
LOW
8
BITS
.
0
X
27
E
ND
P
IXEL
,
HIGH
8
BITS
.
This is the rightmost pixel in the ROI. Pixels are numbered from 0 to the sensor width - 1.
This is different from the old ROI settings which worked in pixel clocks. The sensor control
logic handles the conversion from pixels to clocks. If the ending pixel is not one less than
a multiple of the sensor readout width (10 for MV13 or 16 for MV40) there will be some
postscan pixels in the resultant image. In the future we may want to add logic in the data
FPGA to mask out the postscan pixels.
0
X
28
S
TART
L
INE
,
LOW
8
BITS
.
0
X
29
S
TART
L
INE
,
HIGH
8
BITS
.
This is the top line in the ROI. Lines are numbered from 0 to the sensor height - 1. Only
lines in the ROI are scanned.
0
X
2A
E
ND
L
INE
,
LOW
8
BITS
.
0
X
2B
E
ND
L
INE
,
HIGH
8
BITS
.
This is the bottom line in the ROI. Lines are numbered from 0 to the sensor height - 1.
Only lines in the ROI are scanned.
0
X
2C
L
INE
P
ERIOD
,
LOW
8
BITS
.
0
X
2D
L
INE
P
ERIOD
,
HIGH
8
BITS
.
