38
16
4
Data FPGA initialization data length in bytes
20
1
Camera State to load at power on (1 to 8)
20
357
Reserved for additional header / ID info
377
11
Part Number, ASCII "800??-5????"
388
3
Part Revision, ASCII "010"
391
9
Serial Number, ASCII "XXX??????"
400
128
FPGA bit stream file header from mkbin, Null
terminated string
Table 3 - Flash Memory Header Page
C
AMERA
S
TATE
S
TORAGE
Internal to the Control FPGA all state is saved in a Block RAM. Copies of the current state
can be saved to the flash or uploaded to the host. The current state can also be retrieved
from flash or changed by the host. Only the host has random access to the camera state
and this only when setting state. Reading back the camera state always sends the entire
state to the host.
Table 4
shows the layout of the camera state memory. Except for
sensor reference voltages, multibyte values are little endian.
Byte
Offset
(decimal)
Bytes Description
0
4
C3, 5A, F0, 69 for detecting uninitialized buffers
4
2
Vln2: 14 D9
6
2
Vref1: 14 D9
8
2
Vtest: 20 00
