Fastfame 9W AP Series, Руководство пользователя

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9W
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AP/P + Serial User’s Manual
3-15
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select
Enabled to support compliance with PCI specification
version 2.1.
The Choice: Enabled, Disabled.
On-Chip Video Window Size
Select the on-chip video window size for VGA drive use.
The Choice: 32MB, 64MB, Disabled.
Local Memory Frequency
The item is used to select the Local Memory Frequency.
The Choice: 100MHz, 133MHz.
Initial Display Cache
The item is used to Enabled/Disabled Initial Display Cache.
The Choice: Enabled, Disabled.
CAS # Latency
Select the local memory clock periods.
The Choice: 2, 3.
Paging Mode Control
Select the paging mode control.
The Choice: Open, Close.
RAS-to-CAS Override
Select the display cache clock periods control.
The Choice: Fast, Slow.
RAS# Timing
This item controls RAS# active to Protegra, and refresh to RAS# active delay ( in
local memory clocks).
The Choice: Fast, Slow.
RAS# Precharge Timing
This item controls RAS# precharge (in local memory clocks).
The choice: Fast, Slow.
9W
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AP/P + Serial User’s Manual
3-16
3-6 Integrated Peripherals
OnChip Primary/Secondary PCI IDE
The integrated peripheral controller contains an IDE interface with support for two
IDE channels. Select
Enabled to activate each channel separately.
The choice: Enabled, Disabled.
The four IDE PIO (Programmed Input/Output) fields let you set a PIO mode (0-4)
for each of the four IDE devices that the onboard IDE interface supports. Modes 0
through 4 provide successively increased performance. In Auto mode, the system
automatically determines the best mode for each device.
The choice: Auto, Mode 0, Mode 1, Mode 2, Mode 3, Mode 4.
IDE Primary/Secondary Master/Slave UDMA
Ultra DMA/33 implementation is possible only if your IDE hard drive supports it
and the operating environment includes a DMA driver (Windows 95 OSR2 or a
third-party IDE bus master driver). If your hard drive and your system software
IDE Primary/Secondary Master/Slave PIO