JP14-R-LP & JP14-Q-LP F
ALCOM
GPS R
ECEIVERS
V
ERSION
1.0.0
1 INTRODUCTION
This documentation is relating to the following FALCOM products:
JP14-R-LP
and
JP14-Q-LP
.
1.1 General
Both products are new of highly integrated, low-power GPS products – based on a
0.13 micron CMOS process of the SiRFstarIII (GSC3fLP – architecture) - coming with
single-board solutions and increased to 20 parallel channel receiver. Both units for
the first time combine a complete A-GPS digital baseband processor, RF front end
and 4 megabits of flash memory in a single 10 mm x 24 mm package, providing
manufacturers of cell phones, PDAs and other portable and wireless devices with a
drop-in AGPS solution they can use to deliver real-time location and navigation
capabilities in a simpler, smaller design with extended battery life.
Both units will deliver exceptional sensitivity, low power consumption and extremely
fast time to first fix (TTFF) in a compact, 40-pin BGA packages. The digital section of
both GPS receivers includes a powerful SiRFstarIII-LP core GPS signal processor that
handles all the time critical and low latency acquisition, tracking and reacquisition
tasks autonomously, and a 50-MHz ARM7TDMI processor. All units with the equivalent
of more than 200,000 correlators used for processing signals, enable extremely fast
and deep GPS signal search capabilities; achieving time-to-first-fix in only seconds;
resulting a significant improvement on the GPS performance. They come with an
integrated 4-megabit flash memory, and 1-megabit SRAM memory eliminating the
need for an external flash component and significantly simplifying the routing
associated with integrating a GPS receiver into a board design.
Units delivers major advancements in GPS performance, accuracy, integration,
computing power and flexibility. Each unit has an integrated temperature
compensated crystal oscillator (TCXO). Due to the higher stability of frequency they
offer a high-improved GPS performance. In addition, higher sensitivity allows them
more flexibility on their design, the placement of the antenna and the selection of
the kind of antenna. Both modules continuously track all in view satellites, thus
providing accurate satellite position data. The physical interface to both units
application is made through the provided balls. It is required for controlling the unit,
receiving GPS location data, transferring data and providing power supply line. All
units incorporate 4 megabits of flash memory required for storing the GPS software
and user application programs and 1 megabit of static RAM.
Compared to the JP14-Q-LP, the JP14-R-LP is more optimized for location
applications requiring high performance in a very smaller form factor – just 10 x 24
mm package, ideal for devices with limited on-board processing power. While the
JP14-Q-LP comes more smaller than JP14-R-LP, just 15 x 17 mm package.
The concept architecture for both units builds perfect basis for the design of high-
sensitive, low-power, compact and cost efficient state-of-the-art GPS enabled
system solutions for target platforms such as mobile phones, automotive systems,
portable computing devices, and embedded consumer devices. Both units are also
designed to be entire products such as AVL tracking unit, handheld GPS.
The core of the units is comprised of the GSC3fLP that comes with Digital and RF in a
single chip, and the GSW3 software stored into the on-chip 4-megabit FLASH that is
API compatible with previous GSW2 software.
The internal GSW3 software completes the package providing flexible system
architecture for standalone GPS based products.
Please, consult SiRF (
www.sirf.com
) for special information about the GSC3f SiRFstarIII
chipset.
This confidential document is the property of FALCOM and may not be copied or circulated without permission.
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