JP14-R-LP & JP14-Q-LP F
ALCOM
GPS R
ECEIVERS
V
ERSION
1.0.0
Ball
Name
I/O
Description
Level
35
PWRCTL
O
Control outputs. Do not use, leave it open.
CMOS
36
WAKEUP
O
Control outputs. Do not use, leave it open.
CMOS
37
GPIO10
I/O
General propose input/output
CMOS
38
M-RST
I
Rest the unit, active low
CMOS
39
VDD_RTC
I
Control-line for production test. Do not use, leave it open.
+1.5 V DC
40
ON/OFF
I
Control-line for production test. Do not use, leave it open.
CMOS
Table 1:
Pin assignment of the JP14-R
6.2 Interfaces (balls assignment) of the JP14-Q-LP
Ball
Name
I/O
Description
Level
1
GND_RF
Analogue grounds
2
VANT
I
Power supply for an active antenna
Up to +12 V DC / max. 25
mA
3
GND
Analogue grounds
0 V
4
VCC
5
VCC
I
Main power supply
+ 3.3 V DC
±
5 %
6
VBAT
I
Power for RTC and SRAM
+3 V DC ±5%
7
VCCRF
O
Supply voltage of RF section
+ 2.85 V DC / max. 25 mA
8
M-RST
I
Rest the unit, active low
CMOS
9
VCCGSP3
O
Control output for baseband processor.Do not use, leave
it open.
CMOS
10
PWRCTL
O
Control outputs. Do not use, leave it open.
CMOS
11
BOOTSEL
I
Boots the unit into the Update mode, if it is set to HIGH.
CMOS (=VCC)
12
WAKEUP
O
Control outputs. Do not use, leave it open.
CMOS
13
CS2
O
Control outputs. Do not use, leave it open.
CMOS
14
GPIO1
I/O
General propose input/output
CMOS
15
GPIO0
I/O
General propose input/output
CMOS
16
SDI1
I
Serial Data Input A
CMOS
17
SDO2
O
Serial Data Output B (It is not supported by default
GSW3.1.0)
CMOS
18
SDO1
O
Serial Data Output A
CMOS
19
VDDK
O
Core power at 1.5 V. Do not use, leave it open.
20
SDI2
I
Serial Data Input B (It is not supported by default
GSW3.1.0)
CMOS
21
GPIO10
I/O
General propose input/output
CMOS
22
VDD_RTC
I
Control-line for production test. Do not use, leave it open.
+1.5 V DC
23
T-MARK
O
1 PPS Time Mark Output
CMOS
24
ON/OFF
I
Control-line for production test. Do not use, leave it open.
CMOS
25
NADC_CS
O
Control outputs. Do not use, leave it open.
CMOS
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