FTG Series Programming Manual
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１０
The channel event register records the status change event of the power supply, and the
meaning of each binary bit corresponds to the bit of the channel condition register. The
channel event register can be cleared by the related query command or "*CLS" command.
After clearing, it will restart to record new events.
Standard Event Status Register Group
Standard Event Status Register Group records important events that occur during power
supply analyzing programming commands or executing operations, including Standard
Event register and Standard Event Enable register.
The definition of each bit of the standard event register is compatible with the IEEE 488.2
standard, and the detailed definition is as follows:
Table 2-3 Standard Event Register Bit Explanation
Bit
7
6
5
4
3
2
1
0
Name
rsv
rsv
CME
EXE
DDE
QYE
rsv
OPC
OPC All operations & commands completed
QYE Query Error
DDE Device specific Error
EXE Excecution Error
CME Command Error
Bits in the Standard Event register are automatically cleared by a query of that register (such
as *ESR?) or by sending the *CLS (clear status) command. Querying an event register returns
a decimal value which corresponds to the binary-weighted sum of all bits set in the register.
The Standard Event ENABle register is used to define which bits of the Standard Event
register will latch ESB (bit 5) of the Status Byte register.
Status Byte Register
The Status Byte Register records important states that IEEE 488.2 bus-compatible devices
need to support. Its status bits record whether there are currently unserviced events, errors,
standard events, etc. in the power supply.
The bits definition of the Status Byte Register are fully compatible with IEEE 488.2
specifications, details are as follows:
