Model
MASS 2
Version
V_1.0
Prepared by
H/W
Date
22/01/2008
Subject Technical
Manual Page
17/59
3.1
Processor Core
The Micro-Controller Unit subsystem in MT6225 is built up with a 32-bit RISC core, ARM7EJ-S that is based on the
Von Neumann architecture with a single 32-bit data bus carrying both instructions and data. The memory interface of
ARM7EJ-S is totally compliant to AMBA based bus system. Basically, it can be connected to AHB Bus directly.
3.2
Memory Management
The processor core of MT6225, ARM7EJ-S, supports only memory addressing method for instruction fetch and data
access. It manages a 32bit address space that has addressing capability up to 4GB. System RAM, System ROM ,
Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space, as depicted in
Figure 7.
Figure 7. Memory Layout of MT6225
External Memory Access
To allow external access, the MT6225 outputs 25 bits (A25-A1) of address lines along with 4 selection signals that
correspond to associated memory blocks. That is, MT6225 can support up to 3 MCU addressable external components.
The data width of internal system bus is fixed at 32-bit wide, while the data width of the external components is fixed as
16 bit.
Factory Programming
The configuration for factory programming is shown in Figure 8. Usually the Factory Programming Host connects
with MT6225 via the UART interface. The download speed can be up to 921K bps while MCU is running at 26MHz.
Содержание MASS2
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