EZZE MASS2, Техническое руководство, Страница: 38 / 137

Model MASS 2 Version V_1.0
Prepared by H/W Date 22/01/2008
Subject Technical Manual Page 16/59
3. Micro-Controller Unit Subsystem
Figure 6 illustrates the block diagram of the Micro-Controller Unit Subsystem in MT6225. The Subsystem utilizes a
main 32-bit ARM7EJ-S RISC processor, which plays the role of the main bus master controlling the whole subsystem.
All processor transactions go to code cache first. The code cache controller accesses TCM(72KB memory dedicated to
ARM7EJS core), cache memory, or bus according to the processor’s request address, If the requested content is found in
TCM or in cache, no bus transaction is required. If the code cache hit rate is high enough, bus traffic can be effectively
reduced and processor core performance maximized. In addition to the benefits of reuse of memory contents, code cache
also has a MPU(Memory Protection Unit), which allows cacheable and protection settings of predefined regions. The
contents of code cache are only accessible to MCU, and only MCU instructions are kept in the cache memory.
The MT6228 MCU subsystem supports only memory addressing method. Therefore all components are mapped onto the
MCU 32-bit address space. A Memory Management Unit is employed to allow for a central decode scheme.
The MMU generates appropriate selection signals for each memory-addressed module on the AHB Bus.
External Memory Interface supports both 8-bit and 16-bit devices. Since AHB Bus is 32-bit wide, all the data transfer
Will be converted into several 8-bit or 16-bit cycles depending on the data width of target device. Note that, this interface
is specific to both synchronous and asynchronous components, like Flash, SRAM and parallel LCD. This interface
supports also page and burst mode type of Flash.
Figure 6. Block Diagram of MCU in MT6225