Model
MASS 2
Version
V_1.0
Prepared by
H/W
Date
22/01/2008
Subject Technical
Manual Page
19/59
External Interrupt
This interrupt controller also integrates an External Interrupt Controller that can support up to 4 interrupt tequests
Coming from external sources, the EIMT 0 ~ 3, and 4 WakeUp interrupt requests, i.e. EINT4~7, coming from
peripherals used to inform system to resume the system clock..
Block diagram of external interrupt controller .
3.4
Internal Memory Interface
System Ram
MT6225 provides one 72 KByte size of on-chip memory modules acting as System RAM for data access with low latency.
Such a module is composed of one high speed synchronous SRAMs with AHB Slave Interface connected to the system
backbone AHB Bus, The synchronous SRAM operates on the same clock as the AHB Bus and is organized as 32 bits wide
with 4 byte-write signals capable for byte operations. The SRAM macro has limited repair capability. The yield of SRAM is
improved if the defects inside it can be repaired during testing.
System ROM
The 15K Bytes System ROM is primarily used to store software program for Factory Programming. This module is
composed of high-speed ROM with an AHB Slave Interface connected to a system backbone AHB. The module operates on
the same clock as the AHB and has a 32-bit wide organization.
3.5
External Memory Interface
MT6228 incorporates a powerful and flexible memory controller, External Memory Interface, to connect with a variety of
memory components. This controller provides one generic access scheme for Flash Memory, SRAM, PSRAM and
CellularRAM and another access scheme for MobileRAM. Up to 3 memory banks can be supported simultaneously, BANK0-
BANK2, with a maximum size of 64MB each. Since most of the Flash Memory, SRAM, PSRAM and CellularRAM have
Содержание MASS2
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