ETAS ES5340.2, Руководство пользователя

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ES5340.2 Electric Drive Simulation Board - User’s Guide 117
ETAS Figures
Figures
Fig. 1-1 Components and interfaces of the ES5340.2 ................................................ 8
Fig. 1-2 Inputs and outputs of the FPGA model ......................................................... 9
Fig. 1-3 Front panel of the ES5340.2 Electric Drive Simulation Board
(left: master, right: slave) ............................................................................ 11
Fig. 1-4 Block diagram of the ES5340.2 Electric Drive Simulation Board: Master
ES5340.2-M (top) and slave ES5340.1-S (bottom) ....................................... 12
Fig. 1-5 WEEE Symbol ............................................................................................. 19
Fig. 2-1 Connecting the RPM buses of two boards .................................................. 27
Fig. 3-1 Schematic circuit diagram of the analog outputs......................................... 32
Fig. 3-2 Signals for the resolver................................................................................ 33
Fig. 3-3 Schematic circuit diagram of an analog output configured as "resolver"..... 34
Fig. 3-4 Signals A and B of the sine encoder ............................................................ 34
Fig. 3-5 FPGA model signals as inputs for the analog multiplexer............................. 37
Fig. 3-6 Schematic circuit diagram of a digital output .............................................. 39
Fig. 3-7 Timing for 120° phase-shifted pulses with 180° duration ............................ 40
Fig. 3-8 Schematic circuit diagram of a digital input................................................. 43
Fig. 3-9 Measurement of digital ECU output signals in the configuration "Pull-Up" or
"Pull-Down" using ES5340 for measurement and ES5436.1 as load simulation
45
Fig. 3-10 Block diagram for configuration as H-bridge using ES5340 for measuring
Chan_x and Chan_y ................................................................................... 46
Fig. 3-11 Sync, Clock, Direction and Engine Speed signals ......................................... 47
Fig. 4-1 The modeled system ................................................................................... 49
Fig. 4-2 Measurement and control variables of the inverter ECU .............................. 50
Fig. 4-3 The modeled system ................................................................................... 59
Fig. 6-1 Connectors for the outputs (top view) ........................................................ 98
Fig. 6-2 Connectors for the inputs (top view)........................................................... 99
Fig. 6-3 Connectors for the angle clock signal ....................................................... 101