ESD EPPC-T10, Руководство по оборудованию, Страница: 29 / 37

CPU
7. CPU
The general function of the NXP QorIQ T014 is not described in this manual.
Further information about the CPU can for example be downloaded from the website of the
manufacturer NXP:
http://www.nxp.com/
Base Address Functionality
0xF FE13 3008 GPIO register (see chapter 7.1)
0xF FFD0 0000 Optional MRAM (Customized option on request only.
The optional MRAM is connected to the CPU via the local bus.)
Table 5: Base address
7.1 User configuration via GPIO register
Via CPU GPIO register the settings can be handled as shown in the following table.
Address
Register
name
Bits
31 … … 20 19 ... … 16 15 ... … 13 12 11 … … 8 7 … … 0
0xFE133008 GPIO_4
reserved
SW900
reserved
Reset
Disable
SW901
reserved
Table 6: CPU register GPIO_4
Description
Name Access Description
SW900 ro Read back the setting of the configuration DIP switch SW900
SW901 ro Read back the setting of the configuration DIP switch SW901
NOTICE
Reserved values must be written with the value that is read before.
The switches are equipped on the PCB top layer as described in Figure 2 on page 16.
Read chapter “Configuration via DIP Switch” on page 24 for further information about the switches.
Bit LC_IO SW900 Pin Bit LC_IO SW901 Pin
19 LC_IO12 4 11 LC_IO20 4
18 LC_IO13 3 10 LC_IO21 3
17 LC_IO14 2 9 LC_IO22 2
16 LC_IO15 1 8 LC_IO23 1
7.2 Watchdog
The watchdog is described in the manual:
“EREF: A Programmer’s Reference Manual for Freescale Embedded Processors”.
The manual can be downloaded from the NXP website.
EPPC-T10 Hardware Manual • Doc. No.: I.2007.21 / Rev. 1.1 Page 29 of 37