Software
6. Software
6.1 Configuration and Console Access
Use an USB cable with miniUSB connector (Terminal interface, see EPPC-T10 front panel, page
18) to connect the EPPC-T10 to a PCs USB port. Install the driver if necessary.
Current drivers can be downloaded from :
http://www.ftdichip.com/
.
Now open a terminal program and point to the new COM port of the EPPC-T10.
The default communication parameters are 115 200 baud, 8N1 (8 data bits, no parity, 1 stop-bit, no
hardware handshake).
After power-on you will see the bootloader start-up messages being output on the serial console.
When you see the message 'Press SPACE ....', hit the space key to stop booting and to access the
interactive bootloader console. At the prompt you can use an extensive command set to do
configuration, debugging or testing tasks. Enter help (followed by hitting the RETURN key) to get a
full list of all supported commands.
6.1.1 Start Message
After the connection of the power supply voltage, the Bootloader prompts the message on the
serial console interface (default configuration: 115 200 baud, 8N1):
U-Boot 2016.03.07-17497-g8b3188c-dirty (Sep 18 2017 - 10:24:56 +0200)
CPU0: T1014, Version: 1.1, (0x85210211)
Core: e5500, Version: 2.1, (0x80241021)
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz,
CCB:400 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:66.667 MHz
QE:200 MHz
FMAN1: 400 MHz
QMAN: 200 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0810000c 0c000000 00000000 00000000
00000010: 88000000 00008002 ec027000 21002000
00000020: 00000000 affebaff 00000000 00036760
00000030: 00000200 c1560a04 00000000 00000006
Board: eppct10/T1014, HW: 1
Boot from SPI
SERDES Reference Clocks:
SD1_CLK1=100.00MHZ, SD1_CLK2=125.00MHz
I2C: ready
SPI: ready
DRAM: Detected UDIMM esd_CPU-T10_512MB
Found timing match: n_ranks 1, data rate 1666, rank_gb 0
clk_adjust 10, wrlvl_start 6, wrlvl_ctrl_2 0x708080a, 0 of 1 controllers are interleaving.
512 MiB (DDR3, 64-bit, CL=11, ECC on)
L2: 256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 136 (0x88)
MMC: FSL_SDHC: 0
Bus 0 was idle
Bus 1 was idle
Bus 2 was idle
PCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: Root Complex, no link, regs @ 0xfe250000
PCIe2: Bus 01 - 01
PCIe3: Root Complex, no link, regs @ 0xfe260000
PCIe3: Bus 02 - 02
In: serial
Out: serial
Err: serial
Net: Fman1: Uploading microcode version 106.4.17
Page 26 of 37
Hardware Manual • Doc. No.: I.2007.21 / Rev. 1.1
EPPC-T10