14. Functions
RX8130CE
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ETM50E-07
Seiko Epson Corporation
31
TIE bit
/
IRQ output
TF bit
Event occurs
TE bit
tRTN
tRTN
tRTN
period
period
period
tRTN
period
"
1
"
"
0
"
"
1
"
"
0
"
Hi
-
z
"
L
"
"
1
"
"
0
"
Operation of fixed-cycle timer
I
nternal operation
Write operation
Fixed-cycle timer starts
Fixed-cycle timer stops
Figure 21 Wakeup timer timing chart
(1) A
time update interrupt event occurs when the internal clock's value matches either the second update
time or the minute update time. The USEL bit's specification determines whether it is the second update
time or the minute update time that must be matched.
(2) When a time update interrupt event occurs, the UF bit value becomes "1".
(3)
When the UF bit value is "1" its value is retained until it is cleared to zero.
(4) When a time update interrupt occurs, /IRQ pin output is low if UIE =
"1".
If UIE =
"0" when a timer update interrupt occurs, the /IRQ pin status remains Hi-Z.
(5)
Each time an event occurs, /IRQ pin output is low only up to the tRTN time (which is fixed as min 7.57 ms
for time update interrupts) after which it is automatically cleared to Hi-Z.
/IRQ pin output goes low again when the next interrupt event occurs.
(6)
As long as /IRQ
=
low, the /IRQ pin status does not change, even if the UF bit value changes from "1"
to
"0".
(7)
When /IRQ
=
low, the /IRQ pin status changes from low to Hi-Z as soon as the UIE bit value changes from
"1" to
"0".
