13. Overview of Functions and Registers
RX8130CE
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ETM50E-07
Seiko Epson Corporation
23
6) VLF bit
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0"
to "1" when data loss occurs, such as due to a supply voltage drop.
See [
14.5. Frequency stop detection function]
for the details.
7) STOP bit
This bit is to stop a timekeeping operation. In the case of “STOP bit = 1":
1)
All the update of timekeeping and the calendar operation stops.
With it, an update interrupt event does not occur at an alarm interrupt and the time.
2) The part of the
wakeup timer interrupt function stops.
A count stops the source clock setting of the timer in case of "64 Hz, 1 Hz, 1min, 1h".
3) Note 3: The effect of STOP bit to FOUT functions.
When STOP = "1", 32.768 kHz and 1024 Hz output is possible. But 1 Hz output is disabled.
4) Switchover function cannot work in order that the V
DD
voltage drop detection stops even if a main
power supply falls.
8) RSF bit
This flag bit holds the result of detecting the reset voltage.
13.3.6. Function-related register 2
(
1F
h)
1) SMPTSEL1,SMPTSEL0 bit
Operation time setting of a voltage detector circuit for each power supply pin.
See
15.1. Description of Battery Backup switchover function]
for the details.
2) CHGEN bit
Setting of backup battery charge control (ON/OFF).
3) INIEN bit
Setting of a power switchover function (ON/OFF).
4) RSVSEL bit
Setting of voltage detection level of a VDD pin.
5) BFVSEL1,BFVSEL0 bit
Setting of the full charge detection voltage of a backup battery.
13.3.7. Digital offset register
(
30
h)
1) DTE bit
Setting of a Digital offset function (ON/OFF).
See
for the details.
2) L7
L1 bit
Setting of a Digital offset value.
