
REV.-A
3.2.1 8143 Interface Board
When the
and 20
neutral current loop are in use, the printer will also support the 8143 new serial
interface.
Specifications
Synchronization
Bit rate
Word length
Start bit
Data bit
Parity bit
Stop bit
Signal level (EIA level)
Current loop
Handshaking
Asynchronous
75 to 19,200 BPS
1 bit
7 or 8 bit*
Odd, Even or Non-parity’
1 bit or more
M A R K
=
logical “1“ (–3 to –27
V
)
SPACE = logical “O” (+3 to +27 V)
MARK = logical “1” (current ON)
SPACE
logical “O” (current OFF)
By REV
signal or X-ON/X-OFF code
(Signal polarity can be inverted by jumper setting.)
Can be selected by DIP switch setting on the 8143 board.
NOTE :
The parallel interface cable, if connected, should be disconnected before using the 8143 board because
parallel interface input is used to read jumper settings and DIP switch status.
Jumper Settings
Table
3-2
shows the 8143 interface jumper settings.
Table 3-2. 8143 Jumper Settings
‘ - - - - - 1
Function
J1
ON:
is pulled
+
through 470 ohm resistor.
J2
ON: “TTY
RET” is connected to signal ground.
J3
ON: “TTY RXD” is pulled up to + 12V through 470 ohm resistor.
J 4
J5
ON: “DTR and DCD” are pulled up to + 12V through 4.7K ohm resistor.
JRS
ON
Selects input signal level
JC
OFF
------!
JNOR
Selects polarity to disable ‘
N
MARK
t - - - - i
OFF
SPACE
JREV
data entry
OFF
SPACE (Current loop)
ON
MARK (Current loop)
I
l--i
t--i
O u t p u t s
X
-
O N
/
X
-
O F F
Selects TTY
function
Outputs
flag
OFF
ON
signal
r - - i
3-2
Содержание LQ-1060
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Страница 5: ...REVISION TABLE REVISION DATE ISSUED I CHANGE DOCUMENT I I 1st issue I v ...
Страница 68: ...cc o REV A N N n 1 cc b I al cc u co n4 2 1 Figure 2 14 Main Switching 2 21 ...
Страница 79: ...REV A Table 2 20 State of Module 1 1 I W stay E H H L H d O s H H 4 2 32 ...
Страница 203: ...Figure 5 6 MONPS MONPSE Board Voltage Waveforms 5 17 ...
Страница 204: ...REV A Fiaure 5 6 MONPS MONPSE Board Voltage Waveforms z L 5 18 ...
Страница 205: ...Figure 5 6 MONPS MONPSE Board Voltage Waveforms 5 19 ...
Страница 217: ... n 3 m I BUS CONTROL 1 LJ Pc II SYSTEM CONTROL I I L 1 I PERIPHERAL BUS IIF u lJ Figure A 2 PD78213 Block Diagram A 3 ...
Страница 248: ...REV A A 3 DRAWINGS 3 J32 J TI g 4 Figure A 27 MONPS Board Component Layout A 34 ...
Страница 249: ... J30 33r J32 d m b13 G a TI 7 IC20 r El m J24 C2 L cl mow B L U E u Figure A 28 MONPSE Board Component Layout A 35 ...
Страница 250: ... 2 1 1 1 1 I A b 2 Ozaz 1202 C O ZZH Z UOEE vu I 1 Figure A 29 MONPS Board Circuit Diagram ...
Страница 251: ...REV A 1 UXZO xl OX 9 xl Onz b 8M 118 en A N J 93 T 818 Figure A 30 MONPSE Board Circuit Diagram A 37 ...
Страница 252: ...L t g Figure A 31 JUNMM Board Component Layout A 38 ...