5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Control MCU and FPGA clock
FPGA_CFG_DONE
FPGA_CFG_#PROG
FH_TMS
FH_TCK
FH_TDO
FH_TDI
FH_TRST
GND
GND
GND
GND
GND
GND
GND
GND
GND
FPGA_VCCAUX
FPGA_VCCINT
FPGA_VCCO0
FPGA_VCCO2
FPGA_VCCO3
FPGA_VCCO1
FPGA_VCCAUX
3V3
FPGA_VCCAUX
FPGA_1V2
FPGA_VCCINT
3V3
3V3
3V3
FPGA_CFG_DONE
(p 12)
CTRLMCU_CLK
(p 12)
FPGA_CLK
(p 7)
CTRLMCU_JTAG_TDI
(p 11)
CTRLMCU_JTAG_TMS (p 11)
CTRLMCU_JTAG_TCK (p 11)
CTRLMCU_JTAG_#TRST (p 11)
TEST_#RESET
(p 12)
FPGA_CFG_#PROG
(p 12)
CTRLMCU_JTAG_TDO (p 11)
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C
BRD3200C
Tuesday, January 19, 2010
10
21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Board Control - FPGA Power / Debug
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C
BRD3200C
Tuesday, January 19, 2010
10
21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Board Control - FPGA Power / Debug
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C
BRD3200C
Tuesday, January 19, 2010
10
21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Board Control - FPGA Power / Debug
C41
10N
C41
10N
U7A
24.00MHz
U7A
24.00MHz
OUTPUT
3
OE
1
C60
47U
C60
47U
TP154
TP154
C62
10N
C62
10N
R56
22R
R56
22R
U56C
74LVC2G125DC
U56C
74LVC2G125DC
VCC
8
GND
4
U6E
XC3S200A_4_FT256C_SWAP0
U6E
XC3S200A_4_FT256C_SWAP0
DONE
T15
PROG_B
A2
TCK
A15
TDI
B1
TDO
B16
TMS
B2
VCCAUX
F5
VCCAUX
M6
VCCAUX
E11
VCCAUX
L12
VCCINT
G7
VCCINT
H8
VCCINT
K8
VCCINT
G9
VCCINT
J9
VCCINT
K10
GND
E12
GND
M12
GND
L11
GND
P14
GND
G15
GND
C14
GND
A16
GND
T16
GND
G8
GND
J8
GND
H9
GND
A1
GND
T1
GND
F2
GND
K2
GND
C3
GND
P3
GND
E5
GND
M5
GND
F6
GND
R6
GND
B7
GND
K7
GND
L15
GND
G10
GND
R10
GND
K9
GND
B11
LED81
GREEN
LED81
GREEN
2
1
C61
100N
C61
100N
U57A
74LVC2G125DC
U57A
74LVC2G125DC
2
6
1
RP13
22R
RP13
22R
1
2
3
4
5
6
7
8
TP155
TP155
LED80
YELLOW
LED80
YELLOW
2
1
C56
100N
C56
100N
U56A 74LVC2G125DC
U56A 74LVC2G125DC
2
6
1
C70
100N
C70
100N
C47
10N
C47
10N
C46
10U
C46
10U
R294
22R
NM
R294
22R
NM
R336
0R
R336
0R
R72
0R
R72
0R
C64
100N
C64
100N
C52
10N
C52
10N
C57
10N
C57
10N
C262
100N
C262
100N
C67
100N
C67
100N
C48
100N
C48
100N
R71
470R
R71
470R
R300
33R
R300
33R
C66
10N
C66
10N
C42
100N
C42
100N
U57C
74LVC2G125DC
U57C
74LVC2G125DC
VCC
8
GND
4
C51
10U
C51
10U
C69
47U
C69
47U
R295
47K
R295
47K
U57B
74LVC2G125DC
U57B
74LVC2G125DC
5
7
3
P4
2X5_2.54MM_TH
P4
2X5_2.54MM_TH
1
2
4
8
6
3
5
7
9
10
U56B 74LVC2G125DC
U56B 74LVC2G125DC
5
7
3
C40
100N
C40
100N
C65
100N
C65
100N
R73
0R
R73
0R
R200
22R
R200
22R
C43
100N
C43
100N
U7B
24.00MHz
U7B
24.00MHz
VCC
4
GND
2
C63
10N
C63
10N
R68
470R
R68
470R
C72
10U
C72
10U
R57
100K
R57
100K
RP14
0R
RP14
0R
1
2
3
4
5
6
7
8
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