Endace DAG 4.2S, Руководство пользователя

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EDM01-02: DAG 4.2S Card User Guide
©2005 2 Version 7: May 2006
1.2 DAG 4.2S Card Description
Description The DAG 4.2S single interface OC-48c/STM-16c card is capable of cell
and packet capture and generation on IP networks.
Description Figure 1-1 shows the DAG 4.2S PCI card.
Figure 1-1. DAG 4.2S PCI Card.
1.3 DAG 4.2S Card Architecture
Description Serial SONET optical data is received by the DAG 4.2S card optical
interface, and fed through a demultiplexor into a physical layer ASIC. The
packet data is then fed immediately into the Xilinx FPGA. This FPGA
contains the DUCK timestamp engine, packet record processor, and PCI
interface logic.
The close association of these two components means that packets or cells
can be time-stamped very accurately. Time stamped packet or cell records
are then stored in an external FIFO before transmission to the host.