Endace Measurement Systems Limited
http://www.endace.com
EDM01.05-05r1 DAG 3.6E Card User Manual
Copyright, all rights reserved.
3
Revision 6. 8 August 2005.
1.3 DAG 3.6E Card Series Architecture
, continued
Figure
Figure 1-2 shows the DAG 3.6E card series major components and
process flow.
Figure 1-2. DAG 3.6E Card Series Major Components and Process Flow.
In this section
This section covers the following topics of information.
•
DAG 3.6EP Card Architecture
•
DAG 3.6ET Card Architecture
1.3.1 DAG 3.6EP Card Architecture
Description
The DAG 3.6EP has two independent 10/100 Ethernet interfaces.
Each can be connected to a separate switch or hub, and autonegotiate with
the connected equipment.
Ethernet
framers
Each single half or full-duplex 10 or 100Mbps Ethernet connection passes
into a port of the DAG card. Two Ethernet framers look at data from each
port independently. The DAG card captures from half duplex or full
duplex links.
Packet time
stamping
Serial Ethernet data is received by the interface, and fed through a framer
into the upper of two Xilinx FPGA’s. This FPGA contains an Ethernet
processor and the DUCK timestamp engine.
Because of component close association, packets or cells are time-stamped
accurately. Time stamped packet records are then stored in the lower
FIFO.
Continued on next page
