RELEASED: 10/2/2006
Page 40
COMMUNICATI0NS
HSD SERIES OPERATION AND MAINTENANCE
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3.14 12.5 WATT AMPLIFIER:
P/N 50531000
Schematic Diagram 50531002A, A1PA (S-Band)
Interconnection Diagram 50000002, A2/A3
Gain
(j1-J2)
+20dB
Typical
Power Output (J2)
≈
42dBm Typical
Drain of Q1 & Q2
10.0Vdc
@
1.3Adc
Drains of Q3, Q4, Q5
10.25Vdc
@
7.0Adc
The 12.5 Watt S-Band Amplifier module provides an end-to-end gain of 20dB. The
module contains two amplifier sections; the first section is a 9dB gain distributed
matching element amplifier running class A, and the second section is an 11dB gain
distributed matching and lumped element amplifier also running class A.
The module input at J1 comes from the Output Converter module at a level of
150mW (
≈
22dBm) average power. The J1 input signal line is connected to the 90
degree hybrid splitter CP1 through a printed micro strip line. The splitter exhibits a
throughput loss of 3dB. The network of R1-R4 provides a 50 ohm match for the
isolation port of the splitter. The two outputs of CP1 are equal in amplitude but 90
degrees out of phase. The two splitter outputs feed the circuits of Q1 and Q2 which
are identical. The gate bias circuits of Q1 and Q2 are adjusted by potentiometers
R7 and R9 respectively which adjust the drain currents of Q1 and Q2. To set the
correct drain current for Q1, adjust R7 to set the voltage drop across R37 at 1.95
volts. This sets a drain current of 1.3 amps and a drain voltage of 10 volts. To set
the drain current of Q2, use potentiometer R9 and set the voltage drop across R38
in the same way.
The outputs of the Q1 and Q1 circuits are then combined in phase by coupler CP2
which exhibits a 0.25dB loss. The gain of the circuits between CP1 and CP2 is a
nominal 9dB. The isolated output (J3) of coupler CP2 is loaded by 50 ohm load
R11, and the output side of the coupler connects to the RF input of a three way
micro strip splitter which feeds three identical push-pull FET amplifier circuits.
Each power FET circuit is fed by a 50 ohm balun (CP3-CP5) which receives the
unbalanced 50 ohm input and converts it to a 50 ohm balanced output with each leg
being 180° out of phase. This balanced output drives the dual FET amplifier which
operates as a push-pull amplifier. The gates of Q3 are biased through R14 and R15
by the bias circuit formed around op amp buffer U2. The U2 buffer amplifier has a
gain of 1v/v. The current for the drains of Q3 is set by potentiometer R26. To set
the drain currents for Q3, use potentiometer R26 and set the voltage drop across
R43 at 1.75 volts. This sets an equal gate current of 3.5Adc for each side of the
dual power FET and a gate voltage of between -.8 and -1 volt. All three dual power
