Embedian SMARC-iMX8M Series, Руководство пользователя, Страница: 168 / 174

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SMARC-iMX8M Computer on Module User’s Manual v.1.0
When the RESET_IN# is asserted, a reset cycle is initiated. The module internal
reset and the external reset output RESET_OUT# are asserted as long as
RESET_IN# is asserted. If the reset input RESET_IN# is de‐asserted, the internal
reset and the RESET_OUT# will remain low for at least 1ms until they are also
de‐asserted and the module starts booting again. This guarantees a minimum
reset time of 1ms even if the reset input
RESET_IN# is triggered for a short
time.
Figure 31: Reset Sequence