3 - 10
AM37 Mainboard Manual
System BIOS Cacheable
When enabled, allows the ROM area F000H-FFFFH to be cacheable when
cache controller is activated. The options are: Enabled, Disabled.
Memory Hole
When you install a Legacy ISA card, this feature allows you to select the
memory hole address range of the ISA cycle when the processor accesses
the selected address area. Please read your card manual for detail informa-
tion. When disabled, the memory hole at the (15-16MB) address will be
treated as a DRAM cycle when the processor accesses the15~16MB ad-
dress area. The options are: 15M - 16M, Disabled.
PCI Delay Transaction
Enable this feature to abort the current PCI master cycle and to accept the
new PCI master request, it reaccepts the original PCI master and returns
the PCI data phase to the original PCI master. The options are: Disabled,
Enabled.
CPU & PCI Bus Control
PCI1/2 Master 0 WS Write
When enabled, allows a zero-wait-state-cycle delay when the PCI1/2 mas-
ter drive writes data to DRAM. The options are: Enabled, Disabled.
PCI1/2 Post Write
When enabled, allows the CPU to PCI1/2 master drive excutes post write.
The options are: Enabled, Disabled.
AGP Master 1 WS Write
When enabled, the AGP bus master write access to DRAMs will add one
wait-state cycle. The options are: Enabled, Disabled.
AGP Master 1 WS Read
When enabled, the AGP bus master read access to the DRAMs will add one
wait-state cycle. The options are: Disabled, Enabled.
AGP Fast Write
This feature allows you to set AGP fast write mode.
The options are: Disabled, Enabled.
