Embedded Solutions
Page 8 of 46
Theory of Operation
The Spartan3 FPGA implements the PCI interface for the PMC-XM. Data is transferred
to/from the PCI bus using single-word accesses for control/status or through the four
scatter-gather DMA engines (two in and two out) for accessing the two I/O channels,
each with a 4K x 32-bit transmit FIFO and a 4K x 32-bit receive FIFO.
A data transfer state-machine controls the bidirectional bursting of data between the
Spartan3 and the Virtex for the two I/O channels. The data is transferred across a 32-
bit bidirectional data bus and Virtex control/status registers are addressed by an eight-
bit address bus. The transfers are independently enabled from the Channel Control
Registers in the Spartan3. In the Virtex ATP design used by Dynamic Engineering to
test the PMC-XM hardware, there are also four corresponding 4K x 32-bit FIFOs to
buffer the bursted data. Handshaking signals generated by the Virtex let the transfer
state-machine know when to burst data and, when the FIFOs are near their limits, when
to move only single words.
The plug-in Interface Module is accessed through the Virtex by the user-specified
design with which it is configured. A programmable PLL supplies two independent clock
frequencies (maximum 200 MHz) to be used by the user. Digital clock managers
(DCMs) in the Virtex FPGA can be used to further enhance the clock capabilities. A
1Mx36-bit QDDRII RAM is accessible by the Virtex for intermediate processing of I/O
data and a 13-bit digital temperature sensor can be used to read the ambient
temperature of the PMC-XM environment.
Scatter-gather DMA is accomplished by writing a list of memory descriptors to host
memory. Each descriptor consists of three long-words: the physical address of a block
of contiguous user memory, the length of that block and a pointer to the next list entry.
The last word of each descriptor also contains two flag-bits that are replaced with zeros
for the actual memory access. Bit 0 is the end-of-chain bit. When this bit is set, the
current descriptor is the last in the list. Bit 1 is the direction bit. When this bit is set, it
indicates that the transfer is from the module to host memory. When this bit is zero,
data is transferred from host memory to the PMC-XM.
The address of the first list entry is written to the DMA engine to begin DMA processing.
The DMA continues until the list is complete and an interrupt is signaled to clean-up the
transfer and potentially begin another. It is necessary that all memory pages that are to
be accessed be physically resident in memory while the DMA is in progress.
The four DMA engines can all operate simultaneously. PCI bus access is arbitrated on
a round-robin basis with a DMA engine relinquishing the bus at the end of each list entry
transfer or when the corresponding FIFO gets close to full for the transmit or empty for
the receive. The arbiter can also be configured to give priority to a channel that is
approaching the FIFO limit (almost-empty for the transmit or almost-full for the receive).
