Embedded Solutions
Page 19 of 46
XM_CHAN0/1_WR/RD_DMA_PNTR
[0x0018, 0x001C, 0x0048, 0x004C] DMA Address Register (Write only)
DMA Pointer Address Register
Data Bit
Description
31-0
First Chaining Descriptor Physical Address
FIGURE 8
PMC-XM SPARTAN3 CHANNEL DMA POINTER REGISTER
These write-only ports are used to initiate scatter-gather DMAs. When the physical
address of the first chaining descriptor is written to one of these ports, the
corresponding DMA engine reads three successive long words beginning at that
address. The first is the address of the first memory block of the DMA buffer, the
second is the length in bytes of that block, and the third is the address of the next
chaining descriptor in the list of buffer memory blocks. This process is continued until a
bit in one of the next pointer values read indicates that it is the end of the chain.
Note: Writing a zero to one of these ports will abort the associated DMA if one is in
progress.
XM_CHAN0/1_FIFO
[0x0020, 0x0050] Write TX/Read RX FIFO Port
TX / RX FIFO Port
Data Bit
Description
31-0
FIFO Data 31-0
FIGURE 9
PMC-XM SPARTAN3 CHANNEL FIFO PORT
Data written to this address is written into the transmit FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the receive FIFO. When the
receive FIFO becomes empty, the last data-word that was in the FIFO will be returned.
