Page 9 of 32 Embedded Solutions
The reset switch provided can be used to reset the IP devices without affecting the PCI
bus. Power, PCI reset, and a control register bit also cause the IP Reset to be
activated. The reset is controlled to be synchronous to the 8 MHz. clock. Alternatively,
the IP-Debug-Bus card can be used for individual slot resets.
FIGURE 2
PCI5IP RESET CIRCUIT
The IO are brought to 50 pin headers. The headers are installed without ejectors to be
PCI compliant [height]. The ejectors can be installed by special request. Routing is
matched length, impedance controlled, and differential on a per IP basis. The
differential pairs are 1-2,3-4,..23-24, 25-50, 26-27
…
48-49. With this pattern the
differential pairs can be properly routed for both the IP and Header connectors with
adjacent pin pairs used except for the single 25-50 pair. Frequently 25 and 50 are
grounds. Routing is still 1:1 as well making signal tracing through the carrier easier to
deal with. Dynamic Engineering IP modules take advantage of the differential definition
just outlined.
PCI5IP conforms to the VITA standard for IndustryPack Carriers. This guarantees
compatibility with multiple IndustryPack compatible modules.
PCI5IP conforms to the PCI 2.3 specification and supports both 3.3V and 5V signaling
levels. PCI5IP is accessible in the memory space on the PCI bus. This guarantees
compatibility with other PCI compliant hardware – most PC’s.
The PCI interface is integrated with the IP interface providing superior performance over
designs relying on a separate PCI interface device. In addition to access speed the
higher level of integration results in fewer initialization steps and requirements, more
flexibility in operation, a higher MTBF, and less complex software with only one Base
Address [BAR] to deal with.
If your project can benefit from a "non-standard" implementation, or features that we
have not thought of, or implemented yet please let us know. The Xilinx has room. For
example; if your project will use IP's that can operate at 33 MHz instead of 32, then we
could synchronize the IP and PCI clocks and save several synchronization steps.
C
D
Q
C
D
Q
IP REFERENCE CLK
IP RESET
VCC DETECT TIMER
RESET REG BIT
PUSH BUTTON
