Page 22 of 32 Embedded Solutions
Word Swap
when ‘1’ will cause the upper and lower words to be swapped. Data
written to PCI D15-0 will be driven onto the IP bus as if it originated on D31-16.
Word Swap when ‘0’ leaves the data on the PCI word definitions. Please note
that Word Swap has no effect on 32 bit accesses to 32 bit IP Module ports.
The IP bus interface state-machine will move data from D15-0 to the “0” address
and from PCI D31-16 to the IP “2” address. IP addresses are word based for
non-32 bit capable accesses [even with 32 bit transfers]. The PCI bus will write
data to either the upper or lower words and apply the corresponding CBE byte
lane strobes. The PCI5IP hardware will translate the data to D15-0 on the IP.
Word swapping can be used effectively for big endian
ó
little endian translation
and to accommodate IPs with registers that can be more effectively accessed in
reverse order. For example: if the IP registers are organized with the MS data at
address 0x00 and the LS data at 0x02 then a single 32 bit write can be made to
0x00 with address incrementing enabled and word swapping enabled so that the
PCI D31-16 data is written to IP 0x00 and the PCI D15-0 data is written to IP
0x02. If the IP registers have data 16 bits or less then word swapping will not be
needed.
With the combination of Byte and Word Swapping plus address definition any
byte/word can be direct to/from any destination. Big
ó
little endian issues can
be resolved and IP architecture optimized for software access.
The
bus erro
r bit is a status bit with a write clear. The clear is active at the time
of the write only and does not need to be reset. If the bus error bit is set when
the register is read then a bus error has occurred on this slot. Once set the bit
will remain set until explicitly cleared by writing a ‘1’ to this bit position. This bit
must be cleared to re-arm the Bus Error Interrupt / Master status capability.
