Page 7 of 32 Embedded Solutions
access to that slot.
PCI5IP has a watch-dog timer function which completes the IP access if the IP does not
respond within 7.6 uS. The watch-dog timer has a master status bit and an optional
interrupt output. In addition to the master status each slot control register reports status
for the bus error. Multi-threaded programs can tell if their hardware access caused the
Bus Error even if other threads have accessed other hardware since the bus error was
caused.
The design of PCI5IP tags all accesses from the PCI bus. IP Modules can take longer
than the PCI response specification leading to the use of retry cycles on the PCI bus.
In a single CPU system the retry accesses are done serially. The current IP access will
be the correct one to respond to the retry access. In a multi-CPU system it is possible
to get out of sequence accesses, and potentially have the IP response sent to the
wrong retry access. By storing the PCI parameters for the IP access and only
responding to the correct retry cycle; multiprocessor cross contamination is avoided.
This feature is incorporated beginning with the revision F.
Each slot is programmable for 8 or 32 MHz. operation. The control register has
separate bits for slot A, B, C, D and E. The clocks are locked together and can be
switched at any time. Hardware insures that the clocks switch basis on a clock period
boundary to provide seamless operation.
PCI5IP supports interrupts from each slot with separate mask bits. Two interrupts from
each of the five slots. An interrupt “force” bit is supplied to aide in software
development. The bus error [watch dog timer] can also be an interrupt condition. The
masked interrupts are tied together and connected to INTA on the PCI bus.
PCI5IP has LED's for power, access, and user functions. The supplied voltages are
monitored and an LED illuminated when in tolerance. +12, -12, +5, 3.3. An additional 8
LED's are supplied which are controlled via the control register for user defined
purposes. Five LED’s are controlled by a timer circuit which is activated by the
acknowledge from each of the IP slots.
The power to each of the IP slots is individually filtered and fused for +5 and ±12. The
fuses are rated at 2A on the 5V rail and 1.1A on the ±12V rails. PCI5IP is designed to
route maximum power to each slot in parallel. The power supply capabilities for your
chassis may provide additional constraints. Each slot filter has a separate RF filter, bulk
capacitor, “self healing” fuse, and bipass capacitors. A bipass capacitor is located at
each of the power pins on the PCI5IP with the bulk capacitor near the filter pin for
optimum noise rejection, voltage hold-up and local filtering. For power hungry IP’s the
fuses can be replaced with a strap to allow for more than the specified current.
