Page 10 of 32 Embedded Solutions
Wired but not yet implemented. (1) All of the DMA control signals are available for a
future revision to implement.
Wired and User implemented. The IP Strobe signal is connected from each IP slot to a
5 pin header to allow for inter-slot user defined communications. The IP specification
does not define what the strobe can be used for. The header is rarely used. If you
need it please add “–STB” to your order number and we will install the 5 pin header for
you. Standard .025” sq. posts suitable for wire-wrap inter-connection.
On each IP Slot the Strobe signal is connected to pin 46.
FLASH memory is used to program the FPGA. Future updates can be added to your
card with the Xilinx Impact tool should you want to make use of a new feature. For
example with the Revision G FLASH, the PCI Core is now a Dynamic Engineering
design. This is important because we have corrected a defect in the core previously
used which interfered with use in external chassis.
FLASH Revisions:
Initial Release A 4/2002, ported from PCI3IP and added 2 positions plus independent
controls
Rev B 6/03 Add independent bus error status bits
Rev C 6/03 Add 32 bit addressing and dual slot operation capability
Rev D 7/03 Add byte and word swap capability
Rev E 6/09 Add protection for multi-processor operation
Rev F 8/09 minor update for 32 bit addressing with multi-processor protection
Rev G 4/16 Update to use DE designed PCI core, add Readable Revision field
Rev G.1 7/16 Update to add Bus Error status bits to base status register and master
bus error clear control. Modification to Bus Error capture logic. Addition
of readable FLASH major and minor revision.
Strobe Pinout on Header
TP1
1
STB A
2
STB B
3
STB C
4
STB D
5
STB E
FIGURE 3
PCI5IP STROBE CONNECTION TABLE
